Some semiconductor devices utilize semiconductor-on-insulator (SOI) technology, in which a thin layer of a semiconductor, such as silicon, is separated from a semiconductor substrate or wafer by a relatively thick electrically insulating layer. This thick electrically insulating layer is also referred to as a buried oxide (BOX) layer. The semiconductor layer typically has a thickness of a few nanometers, whereas the semiconductor substrate typically has a thickness of a few tens of nanometers.
SOI technology offer certain advantages compared to traditional bulk technology for Complementary Metal Oxide Semiconductor (CMOS) devices. CMOS devices include nMOSFET transistors and pMOSFET transistors both formed in the thin silicon layer which overlies the buried oxide (BOX) layer. SOI technology allows CMOS devices to operate at lower power consumption while providing the same performance level.
One particular type of SOI technology that is helping to allow for continued CMOS scaling is fully depleted SOI (FDSOI). As opposed to a partially depleted SOI (PDSOI) device, in an FDSOI device a relatively thin semiconductor channel layer is provided over the buried oxide (BOX) layer, such that the depletion region of the device covers the whole layer. FDSOI devices may provide advantages such as higher switching speeds and a reduction in threshold voltage roll off, as compared to PDSOI devices, for example.
To improve CMOS device performance, stress may be introduced into the channels of the field effect transistors (FETs). When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (i.e., n-channel MOSFET drive currents) while compressive stress is known to enhance hole mobility (i.e., p-channel MOSFET drive currents). Consequently, tensile stressed silicon-on-insulator (sSOI) is a main performance driver for nMOSFET transistors, and compressive stressed silicon-germanium-on-insulator (SGOI) is a main performance driver for pMOSFET transistors.
To prevent electrical current leakage between adjacent nMOSFET and pMOSFET transistors in a stressed SOI wafer, a shallow trench isolation (STI) is formed between the two transistors. An STI is generally formed early during the semiconductor device fabrication process before the transistors are formed. To form an STI, a mask layer is formed on the stressed semiconductor layer and an isolation trench is formed through the mask layer and into the SOI wafer between the two active regions corresponding to the adjacent nMOSFET and pMOSFET transistors. A dielectric body is formed in the isolation trench.
As the hard mask is removed, a mechanical relaxation of the stressed semiconductor layer occurs at an edge thereof that contacts the dielectric body in the isolation trench. As illustrated by the semiconductor device 10 in FIG. 1, the mechanical relaxation is elastic and may result in a divot or gap 12 being formed between a sidewall 23 of the stressed semiconductor layer 22 and an adjacent sidewall 17 of the STI 16. The stressed semiconductor layer 22 is part of a stressed SOI wafer 20 that includes a buried oxide layer (BOX) 24 and a semiconductor substrate or wafer 26. A mechanical relaxation of the stressed semiconductor layer 22 negatively effects carrier mobility and transistor threshold voltage variability.